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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the device.  <a href="struct_x_scu_gic___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic.html">XScuGic</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver instance data.  <a href="struct_x_scu_gic.html#details">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga9f2c28f54da589ba1000235cfb0929ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga9f2c28f54da589ba1000235cfb0929ba">XSCUGIC_H</a></td></tr>
<tr class="memdesc:ga9f2c28f54da589ba1000235cfb0929ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="group__scugic__api.html#ga9f2c28f54da589ba1000235cfb0929ba">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">EFUSE status Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>EFUSE Status Register </p>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>EFUSE_STATUS_OFFSET</b>&#160;&#160;&#160;0x10</td></tr>
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<tr class="memitem:gabf7f61958eba005dd02a7014a664def5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabf7f61958eba005dd02a7014a664def5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>EFUSE_STATUS_CPU_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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<tr class="memitem:ga3dde6ae31d569b01dc88903a5340d744"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3dde6ae31d569b01dc88903a5340d744">ARMA9</a></td></tr>
<tr class="memdesc:ga3dde6ae31d569b01dc88903a5340d744"><td class="mdescLeft">&#160;</td><td class="mdescRight">ARMA9 macro to identify cortexA9.  <a href="group__scugic__api.html#ga3dde6ae31d569b01dc88903a5340d744">More...</a><br/></td></tr>
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GICD_CTLR Register information</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp2b456a55406635bf4ed57e8208932672"></a>GICD_CTLR Status Register </p>
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<tr class="memitem:ga8fe68480cb749450b3b8df5af1fb5198"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8fe68480cb749450b3b8df5af1fb5198"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUGIC500_DCTLR_ARE_NS_ENABLE</b>&#160;&#160;&#160;0x20</td></tr>
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<tr class="memitem:ga28dd6678d0630c07191a41b8f5af0950"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga28dd6678d0630c07191a41b8f5af0950"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUGIC500_DCTLR_ARE_S_ENABLE</b>&#160;&#160;&#160;0x10</td></tr>
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<tr class="memitem:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">XScuGic_CPUWriteReg</a>(InstancePtr, RegOffset, Data)</td></tr>
<tr class="memdesc:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given CPU Interface register.  <a href="group__scugic__api.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">More...</a><br/></td></tr>
<tr class="separator:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">XScuGic_CPUReadReg</a>(InstancePtr, RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset)))</td></tr>
<tr class="memdesc:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the given CPU Interface register.  <a href="group__scugic__api.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">More...</a><br/></td></tr>
<tr class="separator:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>(InstancePtr, RegOffset, Data)</td></tr>
<tr class="memdesc:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given Distributor Interface register.  <a href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">More...</a><br/></td></tr>
<tr class="separator:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d639fe1851f9d833367fb4322390eeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>(InstancePtr, RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset)))</td></tr>
<tr class="memdesc:ga3d639fe1851f9d833367fb4322390eeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the given Distributor Interface register.  <a href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">More...</a><br/></td></tr>
<tr class="separator:ga3d639fe1851f9d833367fb4322390eeb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3de9d984ad4026ce214e09bf796cdc49"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a> []</td></tr>
<tr class="memdesc:ga3de9d984ad4026ce214e09bf796cdc49"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config table.  <a href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">More...</a><br/></td></tr>
<tr class="separator:ga3de9d984ad4026ce214e09bf796cdc49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48f9dd531aa861a74e6bd627943573ea"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="memdesc:ga48f9dd531aa861a74e6bd627943573ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.  <a href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">More...</a><br/></td></tr>
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<tr class="memitem:gad162acedbbd41fd890fc7f2225ed480b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gad162acedbbd41fd890fc7f2225ed480b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id.  <a href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">More...</a><br/></td></tr>
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<tr class="memitem:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gac965b9e3ae7668a92cf07a65bde142cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt source provided as the argument Int_Id.  <a href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">More...</a><br/></td></tr>
<tr class="separator:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafd153e16238a1189c513846675e096a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gaafd153e16238a1189c513846675e096a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id.  <a href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">More...</a><br/></td></tr>
<tr class="separator:gaafd153e16238a1189c513846675e096a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, <a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
<tr class="memdesc:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CfgInitialize a specific interrupt controller instance/driver.  <a href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">More...</a><br/></td></tr>
<tr class="separator:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca28a576540ab5fcd75cee1f38917ae4"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u32 Cpu_Identifier)</td></tr>
<tr class="memdesc:gaca28a576540ab5fcd75cee1f38917ae4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Allows software to simulate an interrupt in the interrupt controller.  <a href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">More...</a><br/></td></tr>
<tr class="separator:gaca28a576540ab5fcd75cee1f38917ae4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="memdesc:ga6ed162180ffb45b082c2fbe23951ba13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">More...</a><br/></td></tr>
<tr class="separator:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79abd6248cb578142e9c475f20dbeb06"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="memdesc:ga79abd6248cb578142e9c475f20dbeb06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the interrupt priority and trigger type for the specificd IRQ source.  <a href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">More...</a><br/></td></tr>
<tr class="separator:ga79abd6248cb578142e9c475f20dbeb06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a94f1a519d965f051d598e5a6b5a855"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)</td></tr>
<tr class="memdesc:ga2a94f1a519d965f051d598e5a6b5a855"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the target CPU for the interrupt of a peripheral.  <a href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">More...</a><br/></td></tr>
<tr class="separator:ga2a94f1a519d965f051d598e5a6b5a855"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04f8ea74458251784b293e4ad98f2d74"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)</td></tr>
<tr class="memdesc:ga04f8ea74458251784b293e4ad98f2d74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps specific SPI interrupt from the target CPU.  <a href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">More...</a><br/></td></tr>
<tr class="separator:ga04f8ea74458251784b293e4ad98f2d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66b2416be64a5e582e530ed9ed7f962c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">XScuGic_UnmapAllInterruptsFromCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier)</td></tr>
<tr class="memdesc:ga66b2416be64a5e582e530ed9ed7f962c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps all SPI interrupts from the target CPU.  <a href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">More...</a><br/></td></tr>
<tr class="separator:ga66b2416be64a5e582e530ed9ed7f962c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6146a0489a1c748ceeaee729639d48a7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga6146a0489a1c748ceeaee729639d48a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks if the interrupt target register contains all interrupts to be targeted for current CPU.  <a href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">More...</a><br/></td></tr>
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<tr class="memitem:ga945e029b4356be809020c81745c4a23b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga945e029b4356be809020c81745c4a23b">XScuGic_SetCpuID</a> (u32 CpuCoreId)</td></tr>
<tr class="memdesc:ga945e029b4356be809020c81745c4a23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Updates the CpuId global variable.  <a href="group__scugic__api.html#ga945e029b4356be809020c81745c4a23b">More...</a><br/></td></tr>
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<tr class="memitem:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6c30ba79ea9505dc29b9cac4deea3df8">XScuGic_GetCpuID</a> (void)</td></tr>
<tr class="memdesc:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the CpuId variable.  <a href="group__scugic__api.html#ga6c30ba79ea9505dc29b9cac4deea3df8">More...</a><br/></td></tr>
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<tr class="memitem:ga72b9aec992716861e5f0929e4d0d9f7c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga72b9aec992716861e5f0929e4d0d9f7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks whether the XScGic is initialized or not given the device ID.  <a href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">More...</a><br/></td></tr>
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<tr class="memitem:gab2c0554b809121cc91a96fcd8c749c25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:gab2c0554b809121cc91a96fcd8c749c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the unique device ID.  <a href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">More...</a><br/></td></tr>
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<tr class="memitem:ga805a47295123177a48b07fccfe037702"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga805a47295123177a48b07fccfe037702">XScuGic_LookupConfigBaseAddr</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga805a47295123177a48b07fccfe037702"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the BaseAddress.  <a href="group__scugic__api.html#ga805a47295123177a48b07fccfe037702">More...</a><br/></td></tr>
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<tr class="memitem:gaa26a952ecd376be0bc3d8433023d1364"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa26a952ecd376be0bc3d8433023d1364"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the primary interrupt handler for the driver.  <a href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">More...</a><br/></td></tr>
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<tr class="memitem:ga081a9a62546b413d94e609894282a575"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga081a9a62546b413d94e609894282a575"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">More...</a><br/></td></tr>
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